Senior Verification Engineer (UVM/SystemVerilog) @ Square One Resources v Česko

Odpovědnosti

Původní popisek. 

1. Perform the full range of functional verification activities.
2. Develop verification environments from scratch, including drivers, monitors, scoreboards, and coverage models.
3. Integrate Verification IPs (VIPs) for protocols such as DDR, PCIe, and AXI.
4. Define and implement verification sequences for complex control-flow scenarios.
5. Gain a system-level understanding of products with strong hardware-software interaction.
6. Integrate and maintain reference models.

Ukázat vše (8)

O pozici / o projektu

Původní popisek.  We're looking for Senior Verification Engineer to join our client's project

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